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52307hkim 20070123-s00009 no.8298-1/23 ver.3.00 LC87F5G32A overview the sanyo LC87F5G32A is an 8-bit microcomputer that, centered around a cpu running at a minimum bus cycle time of 100ns, integrates on a single chip a number of hardware features such as 32k-byte flash rom (onboard programmable), 1024-byte ram, an on-chip debugger, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit pwms), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, a synchronous sio interface (with automatic block transmission/reception capabilities) , an asynchronous/synchronous sio interface, a uart interface (full duplex), a 12-bit/8-bit 12-channel ad conv erter, two 12-bit pwm channels, a system clock frequency divider, and a 22-source 10-vector interrupt feature. features ? flash rom ? capable of on-board-programming with wide range, 3.0 to 5.5v, of voltage source. ? block-erasable in 128 byte units ? 32768 8-bits (LC87F5G32A) ? ram ? 1024 9 bits (LC87F5G32A) ? minimum bus cycle ? 100ns (10mhz) note : the bus cycle time here refers to the rom read speed. ? minimum instruction cycle time ? 300ns (10mhz) ordering number : en8298b cmos ic from 32k byte, ram 1024 byte on-chip 8-bit 1-chip microcontroller * this product is licensed from silicon storage te chnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd. specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
LC87F5G32A no.8298-2/23 ? ports ? normal withstand voltage i/o ports ports whose i/o direction can be designated in 1-bit units 30 (p1n,p2n,p30 to p36,p70 to p73,pwm0,pwm1,xt2) ports whose i/o direction can be designated in 4-bit units 8 (p0n) ? normal withstand voltage input port 1 (xt1) ? dedicated oscillator ports 2 (cf1, cf2) ? reset pins 1 ( res ) ? power pins 6 (v ss 1 to 3, v dd 1 to 3) ? timers ? timer 0: 16-bit timer/counter with a capture register. mode 0: 8-bit timer with an 8-bit programmab le prescaler (with an 8-bit capture register) 2-channels mode 1: 8-bit timer with an 8-bit programmable pres caler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) mode 3: 16-bit counter (with a 16-bit capture register) ? timer 1: 16-bit timer/counter that supports pwm/toggle outputs mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + with an 8-bit prescaler 8-bit timer/counter (with toggle outputs) mode 1: 8-bit pwm with an 8-bit prescaler 2-channels mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8-bits) mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (the lower-order 8-bits can be used as pwm.) ? timer 4: 8-bit timer with a 6-bit prescaler ? timer 5: 8-bit timer with a 6-bit prescaler ? timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs) ? timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs) ? base timer 1) the clock is selectable from the subclock (32.768khz crystal oscillation), system clock, and timer 0 prescaler output. 2) interrupts programmable in 5 different time schemes ? high-speed clock counter 1) can count clocks with a maximum clock rate of 20mhz (at a main clock of 10mhz). 2) can generate output real-time. ? sio ? sio0: 8-bit synchronous serial interface 1) lsb first/msb first mode selectable 2) built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3 tcyc) 3) automatic continuous data transmission (1 to 256-bits, specifiable in 1 bit units, suspension and resumption of data transmission possible in 1 byte units) ? sio1: 8-bit asynch ronous/synchronous serial interface mode 0: synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clocks) mode 1: asynchronous serial i/o (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tcyc baudrates) mode 2: bus mode 1 (start bit, 8 data bits, 2 to 512 tcyc transfer clocks) mode 3: bus mode 2 (start detect, 8 data bits, stop detect) ? uart ? full duplex ? 7/8/9 bit data bits selectable ? 1stop bit (2-bit in continuous data transmission) ? built-in baudrate generator ? ad converter: 12-bits/8-bits 12-channels ? 12-bits/8-bits ad converter selectable ? automatic reference voltage generation controllable
LC87F5G32A no.8298-3/23 ? pwm: multifrequency 12-bit pwm 2-channels ? remote control receiver circuit (sharing pins with p73, int3, and t0in) ? noise rejection function (noise filter time constant selectable from 1 tcyc, 32 tcyc, and 128 tcyc) ? watchdog timer ? external rc watchdog timer ? interrupt and reset signals selectable ? interrupts ? 22 sources, 10 vector addresses 1) provides three levels (low (l), high (h), and highest (x)) of multiplex interrupt contro l. any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/int4 4 0001bh h or l int3/int5/base timer 5 00023h h or l t0h 6 0002bh h or l t1l/t1h 7 00033h h or l sio0/uart1 receive 8 0003bh h or l sio1/uart1 transmit 9 00043h h or l adc/t6/t7 10 0004bh h or l port 0/t4/t5/pwm0, pwm1 ? priority levels: x > h > l ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? subroutine stack levels: 512 levels (the stack is allocated in ram.) ? high-speed multiplication/division instructions ? 16-bits 8-bits (5 tcyc execution time) ? 24-bits 16-bits (12 tcyc execution time) ? 16-bits 8-bits (8 tcyc execution time) ? 24-bits 16-bits (12 tcyc execution time) ? oscillation circuits ? rc oscillation circuit (internal): for system clock ? cf oscillation circuit: for system clock, with internal rf ? crystal oscillation circuit: for low-spee d system clock, with internal rf ? frequency variable rc oscillation circuit (internal): for system clock ? system clock divider function ? can run on low current. ? the minimum instruction cycle selectable from 300ns, 600ns, 1.2 s, 2.4 s, 4.8 s, 9.6 s, 19.2 s, 38.4 s, and 76.8 s (at a main clock rate of 10mhz).
LC87F5G32A no.8298-4/23 ? standby function ? halt mode : halts instruction execution while allowing the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) canceled by a system reset or occurrence of an interrupt. ? hold mode : suspends instruction execution an d the operation of the peripheral circuits. 1) the cf, rc, and crystal oscilla tors automatically stop operation. 2) there are three ways of resetting the hold mode. (1) setting the reset pin to the lower level. (2) setting at least one of the int0, int1, int2, int4, and int5 pins to the specified level. (3) having an interrupt source established at port 0. ? x'tal hold mode : suspends instruction execution and the oper ation of the peripheral circuits except the base timer. 1) the cf and rc oscillators automatically stop operation. 2) the state of crystal oscillation established wh en the x'tal hold mode is entered is retained. 3) there are four ways of resetting the x'tal hold mode. (1) setting the reset pin to the low level. (2) setting at least one of the int0, int1, int2, int4, and int5 pins to the specified level. (3) having an interrupt source established at port. (4) having an interrupt source established in the base timer circuit. ? onchip debugger ? supports software debugging with the ic mounted on the target board. ? package form ? qip48e(14 14): ?lead-free type? ? sqfp48(7 7): ?lead-free type? ? development tools ? evaluation chip: lc87ev690 ? emulator: eva62s + ecb876600d + sub875g00 + pod48qfp ice-b877300 + sub875g00 + pod48qfp ? onchip debugger: tcb87 typea + LC87F5G32A tcb87 typeb + LC87F5G32A ? flash rom programming boards package programming boards qip48e(14 14) w87f55256q sqfp48(7 7) w87f55256sq ? flash rom programmer maker model supported version (note) device single af9708/af9709/ af9709b after 02.40 af9723 (main body) after 02.04 flash support group, inc. (formerly ando electric co., ltd.) gang af9833 (unit) after 01.84 LC87F5G32A fast sanyo skk (sanyo fws) after 1.02c (install cd) LC87F5G32A note: please check the latest version. ? same package and pin assignment as mask rom version. 1) lc875g00 series options can be set by using flash rom data. thus the board used for mass production can be used for debugging and evaluation without modifications. 2) if the program for the mask rom version is used, the usable rom/ram capacity is the same as the mask rom version.
LC87F5G32A no.8298-5/23 package dimensions package dimensions unit : mm (typ) unit : mm (typ) 3156a 3163b pin assignment sanyo: qip48e(14 14) "lead-free type" sanyo: sqfp48(7 7) "lead-free type" top view p73/int3/t0in res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p27/int5/t1in p26/int5/t1in p25/int5/t1in p24/int5/t1in p23/int4/t1in p22/int4/t1in p21/urx/int4/t1in p20/utx/int4/t1in p07/t7o/an7 p06/t6o/an6 p05/cko/an5 p04/an4 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 p36 p35 v dd 3 v ss 3 p34 p33 p32/dbgp2 p31/dbgp1 p30/dbgp0 p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in 24 23 22 21 20 19 18 17 16 15 14 13 p03/an3 p02/an2 p01/an1 p00/an0 v ss 2 v dd 2 pwm0 pwm1 p17/t1pwmh/buz p16/t1pwml p15/sck1 p14/si1/sb1 37 38 39 40 41 42 43 44 45 46 47 48 lc87f5g32 a sanyo : qip48e(14x14) 14.0 17.2 14.0 17.2 0.15 0.35 0.8 1.0 (1.5) 1 12 13 24 25 36 37 48 (2.7) 3.0max 0.1 sanyo : sqfp48(7x7) 7.0 7.0 9.0 9.0 0.15 0.5 (1.5) 0.1 1.7max 0.18 0.5 (0.75) 112 13 24 25 36 37 48
LC87F5G32A no.8298-6/23 sqfp/qip name sqfp/qip name 1 p73/int3/t0in 25 p04/an4 2 res 26 p05/cko/an5 3 xt1/an10 27 p06/t6o/an6 4 xt2/an11 28 p07/t7o/an7 5 v ss 1 29 p20/utx/int4/t1in 6 cf1 30 p21/urx/int4/t1in 7 cf2 31 p22/int4/t1in 8 v dd 1 32 p23/int4/t1in 9 p10/so0 33 p24/int5/t1in 10 p11/si0/sb0 34 p25/int5/t1in 11 p12/sck0 35 p26/int5/t1in 12 p13/so1 36 p27/int5/t1in 13 p14/si1/sb1 37 p36 14 p15/sck1 38 p35 15 p16/t1pwml 39 v dd 3 16 p17/t1pwmh/buz 40 v ss 3 17 pwm1 41 p34 18 pwm0 42 p33 19 v dd 2 43 p32/dbgp2 20 v ss 2 44 p31/dbgp1 21 p00/an0 45 p30/dbgp0 22 p01/an1 46 p70/int0/t0lcp/an8 23 p02/an2 47 p71/int1/t0hcp/an9 24 p03/an3 48 p72/int2/t0in
LC87F5G32A no.8298-7/23 system block diagram interrupt control standby control ir pla bus interface port 0 port 1 sio0 sio1 timer 0 timer 1 timer 4 timer 5 port 3 port 7 adc alu flash rom pc acc b register c register psw rar ram stack pointer watchdog timer pwm0 port 2 base timer timer 6 int0-2, int4,5 int3 (noise filter) timer 7 pwm1 clock generator cf rc x?tal mrc on-chip debugger uart1
LC87F5G32A no.8298-8/23 pin function chart pin name i/o description option v ss 1 v ss 2 v ss 3 - - power supply pin yes v dd 1 v dd 2 v dd 3 - + power supply pin no port 0 p00 to p07 i/o ? 8-bit i/o port ? i/o specifiable in 4-bit units ? pull-up resistors can be turned on and off in 4-bit units ? hold reset input ? port 0 interrupt input ? shared pins p05: system clock output p06: timer 6 toggle output p07: timer 7 toggle output ad converter input port: an0 (p00) to an7 (p07) yes port 1 p10 to p17 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units ? pin functions p10: sio0 data output p11: sio0 data input/bus i/o p12: sio0 clock i/o p13: sio1 data output p14: sio1 data input/bus i/o p15: sio1 clock i/o p16: timer 1pwml output p17: timer 1pwmh output/beeper output yes port 2 ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units ? pin functions p20: uart transmit p21: uart receive p20 to p23: int4 input/hold reset input/timer 1 event input/ timer 0l capture input/timer 0h capture input p24 to p27: int5 input/hold reset input/timer 1 event input/ timer 0l capture input/timer 0h capture input interrupt acknowledge type rising falling rising & falling h level l level int4 int5 enable enable enable enable enable enable disable disable disable disable p20 to p27 i/o yes continued on next page.
LC87F5G32A no.8298-9/23 continued from preceding page. pin name i/o description option port 3 p30 to p36 i/o ? 7-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units ? shared pins on-chip debugger pins: dbgp0 to dbgp2 (p30 to p32) yes port 7 ? 4-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units ? shared pins ad converter input port : an8 (p70), an9 (p71) p70: int0 input/hold reset input/time r 0l capture input/watchdog timer output p71: int1 input/hold reset i nput/timer 0h capture input p72: int2 input/hold reset input/time r 0 event input/timer 0l capture input p73: int3 input (with noise filter)/time r 0 event input/timer 0h capture input interrupt acknowledge type rising falling rising & falling h level l level int0 int1 int2 int3 enable enable enable enable enable enable enable enable disable disable enable enable enable enable disable disable enable enable disable disable p70 to p73 i/o no pwm0, pwm1 i/o ? pwm0 and pwm1 output ports ? general-purpose i/o available no res input reset pin no xt1 input ? 32.768khz crystal oscillator input pin ? shared pins general-purpose input port ad converter input port: an10 must be connected to v dd 1 if not to be used no xt2 i/o ? 32.768khz crystal oscillator output pin ? shared pins general-purpose i/o port ad converter input port: an11 must be set for oscillation and kept open if not to be used no cf1 input ceramic resonator input pin no cf2 output ceramic resonator output pin no
LC87F5G32A no.8298-10/23 port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of option type output type pull-up resistor 1 cmos programmable (note 1) p00 to p07 1-bit 2 nch-open drain no 1 cmos programmable p10 to p17 1-bit 2 nch-open drain programmable 1 cmos programmable p20 to p27 1-bit 2 nch-open drain programmable 1 cmos programmable p30 to p36 1-bit 2 nch-open drain programmable p70 - no nch-open drain programmable p71 to p73 - no cmos programmable pwm0, pwm1 - no cmos no xt1 - no input for 32.768khz crystal oscillator (input only) no xt2 - no output for 32.768khz crystal oscillator (nch-open drain when in general-purpose output mode) no note 1: programmable pull-up resistor of port 0 is sp ecified in nibble units (p00 to p03, p04 to p07). note: to reduce v dd signal noise and to increase the duration of the backup battery supply, v ss 1, v ss 2, and v ss 3 should connect to each other and they should also be grounded. example 1: during backup in hold mode, port output ?h? level is supplied from the back-up capacitor. example 2: during backup in hold mode, output is not held high and its value in unsettled. lsi v ss 1 v ss 2 v ss 3 v dd 1 v dd 2 v dd 3 power supply back-up capacitor v ss 1v ss 2v ss 3 v dd 1 v dd 2 v dd 3 power supply back-up capacitor lsi
LC87F5G32A no.8298-11/23 absolute maximum ratings at ta = 25c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit maximum supply voltage v dd max v dd 1, v dd 2, v dd 3 v dd 1=v dd 2=v dd 3 -0.3 +6.5 input voltage vi xt1, cf1 -0.3 v dd +0.3 input/output voltage vio ports 0, 1, 2, 3 port 7, pwm0, pwm1, xt2 -0.3 v dd +0.3 v ioph(1) ports 0, 1, 2, 3 cmos output select per 1 applicable pin -10 ioph(2) pwm0, pwm1 cmos output select per 1 applicable pin -20 peak output current ioph(3) ports p71 to p73 per 1 applicable pin -5 iomh(1) ports 0, 1, 2, 3 cmos output select per 1 applicable pin -7.5 iomh(2) pwm0, pwm1 cmos output select per 1 applicable pin -15 mean output current (note 1-1) iomh(3) ports p71 to p73 per 1 applicable pin -3 ioah(1) ports p71 to p73 total of all applicable pins -10 ioah(2) port 0 total of all applicable pins -25 ioah(3) ports 1, pwm0, pwm1 total of all applicable pins -25 ioah(4) ports 0, 1 pwm0, pwm1 total of all applicable pins -45 ioah(5) ports 2, p35, p36 total of all applicable pins -25 ioah(6) ports p30 to p34 total of all applicable pins -25 high level output current total output current ioah(7) ports 2, 3 total of all applicable pins -45 iopl(1) ports p02 to p07 ports 1, 2, 3 pwm0, pwm1 per 1 applicable pin 20 iopl(2) ports p00, p01 per 1 applicable pin 30 peak output current iopl(3) port 7, xt2 per 1 applicable pin 10 ioml(1) ports p02 to p07 ports 1, 2, 3 pwm0, pwm1 per 1 applicable pin 15 ioml(2) ports p00, p01 per 1 applicable pin 20 mean output current (note 1-1) ioml(3) port 7, xt2 per 1 applicable pin 7.5 ioal(1) port 7, xt2 total of all applicable pins 15 ioal(2) port 0 total of all applicable pins 45 ioal(3) ports 1, pwm0, pwm1 total of all applicable pins 45 ioal(4) ports 0, 1 pwm0, pwm1 total of all applicable pins 80 ioal(5) ports 2, p35, p36 total of all applicable pins 45 ioal(6) ports p30 to p34 total of all applicable pins 45 low level output current total output current ioal(7) ports 2, 3 total of all applicable pins 60 ma sqfp48(7 7) 190 power dissipation pd max qip48e(14 14) ta= -30 to +70 c 390 mw operating ambient temperature topr -30 +70 storage ambient temperature tstg -55 +125 c note 1-1: the mean output current is a mean value measured over 100ms.
LC87F5G32A no.8298-12/23 allowable operating conditions at at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit v dd (1) 0.294 s tcyc 200 s 4.0 5.5 v dd (2) 0.367 s tcyc 200 s 3.0 5.5 operating supply voltage (note 2-1) v dd (3) v dd 1=v dd 2=v dd 3 0.588 s tcyc 200 s 2.5 5.5 memory sustaining supply voltage vhd v dd 1=v dd 2=v dd 3 ram and register contents sustained in hold mode. 2.0 5.5 v ih (1) ports 1, 2, 3 p71 to p73 p70 port input/ interrupt side pwm0, pwm1 2.5 to 5.5 0.3v dd +0.7 v dd v ih (2) port 0 2.5 to 5.5 0.3v dd +0.7 v dd v ih (3) port 70 watchdog timer side 2.5 to 5.5 0.9v dd v dd high level input voltage v ih (4) xt1, xt2, cf1, res 2.5 to 5.5 0.75v dd v dd 4.0 to 5.5 v ss 0.1v dd +0.4 v il (1) ports 1, 2, 3 p71 to p73 p70 port input/ interrupt side pwm0, pwm1 2.5 to 4.0 v ss 0.2v dd 4.0 to 5.5 v ss 0.15v dd +0.4 v il (2) port 0 2.5 to 4.0 v ss 0.2v dd v il (3) port 70 watchdog timer side 2.5 to 5.5 v ss 0.8v dd -1.0 low level input voltage v il (4) xt1, xt2, cf1, res 2.5 to 5.5 v ss 0.25v dd v 4.0 to 5.5 0.294 200 3.0 to 5.5 0.367 200 instruction cycle time (note 2-1) tcyc (note 2-2) 2.5 to 5.5 0.588 200 s 4.0 to 5.5 0.1 10 ? cf2 pin open ? system clock frequency division ratio=1/1 ? external system clock duty=50 5% 2.5 to 5.5 0.1 5 4.0 to 5.5 0.2 20.4 external system clock frequency fexcf cf1 ? cf2 pin open ? system clock frequency division ratio=1/2 2.5 to 5.5 0.1 10 mhz fmcf(1) cf1, cf2 10mhz ceramic oscillation see fig 1. 4.0 to 5.5 10 fmcf(2) cf1, cf2 8mhz ceramic oscillation see fig 1. 3.0 to 5.5 8 fmcf(3) cf1, cf2 5mhz ceramic oscillation see fig 1. 2.5 to 5.5 5 fmrc internal rc oscillation 2.5 to 5.5 0.3 1.0 2.0 fmmrc frequency variable rc oscillation source oscillation 2.5 to 5.5 16 mhz oscillation frequency range (note 2-3) fsx?tal xt1, xt2 32.768khz crystal oscillation see fig 2. 2.5 to 5.5 32.768 khz note 2-1: v dd must be held greater than or equal to 3.0v in the flash rom onboard programming mode. note 2-2: relationship between tcyc and oscillation frequency is 3/fmcf at a division ratio of 1/1 and 6/fmcf at a division ratio of 1/2. note 2-3: see tables 1 and 2 for the oscillation constants.
LC87F5G32A no.8298-13/23 electrical characteristics at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit i ih (1) ports 0, 1, 2, 3 port 7 res pwm0, pwm1 output disabled pull-up resistor off v in =v dd (including output tr's off leakage current) 2.5 to 5.5 1 i ih (2) xt1, xt2 for input port specification v in =v dd 2.5 to 5.5 1 high level input current i ih (3) cf1 vin=v dd 2.5 to 5.5 15 i il (1) ports 0, 1, 2, 3 port 7 res pwm0, pwm1 output disabled pull-up resistor off v in =v ss (including output tr's off leakage current) 2.5 to 5.5 -1 i il (2) xt1, xt2 for input port specification v in =v ss 2.5 to 5.5 -1 low level input current i il (3) cf1 v in =v ss 2.5 to 5.5 -15 a v oh (1) i oh = -1ma 4.5 to 5.5 v dd -1 v oh (2) ports 0, 1, 2, 3 i oh = -0.1ma 2.5 to 5.5 v dd -0.5 v oh (3) p71 to p73 i oh = -0.4ma 4.5 to 5.5 v dd -1 v oh (4) i oh = -6ma 4.5 to 5.5 v dd -1 v oh (5) i oh = -1.6ma 4.5 to 5.5 v dd -0.4 high level output voltage v oh (6) pwm0, pwm1, p05(system clock output function used) i oh = -1ma 2.5 to 5.5 v dd -0.4 v ol (1) i ol =10ma 4.5 to 5.5 1.5 v ol (2) i ol =1.6ma 4.5 to 5.5 0.4 v ol (3) ports 0, 1, 2, 3, pwm0, pwm1, xt2 i ol =1ma 2.5 to 5.5 0.4 v ol (4) p00, p01 i ol =30ma 4.5 to 5.5 1.5 low level output voltage v ol (5) port 7 i ol =1ma 2.5 to 5.5 0.4 v rpu(1) ports 0, 1, 2, 3 port 7 v oh =0.9v dd 4.5 to 5.5 15 35 80 pull-up resistance rpu(2) ports 0, 1, 2, 3 port 7 v oh =0.9v dd 2.5 to 4.5 18 50 150 k ? hysteresis voltage vhys res ports 1, 2, 7 2.5 to 5.5 0.1v dd v pin capacitance cp all pins for pins other than that under test: v in =v ss f=1mhz ta=25 c 2.5 to 5.5 10 pf
LC87F5G32A no.8298-14/23 serial input/output characteristics at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v 1. sio0 serial i/o characteristics (note 4-1-1) specification parameter symbol pin/remarks conditions v dd [v] min typ max unit frequency tsck(1) 2 low level pulse width tsckl(1) 1 tsckh(1) see fig. 6. 1 input clock high level pulse width tsckha(1) sck0(p12) ? continuous data transmission/reception mode ? see fig. 6. ? (note 4-1-2) 2.5 to 5.5 4 frequency tsck(2) 4/3 tcyc low level pulse width tsckl(2) 1/2 tsckh(2) ? cmos output selected ? see fig. 6. 1/2 tsck serial clock output clock high level pulse width tsckha(2) sck0(p12) ? continuous data transmission/reception mode ? cmos output selected ? see fig. 6. 2.5 to 5.5 tsckh(2) +2tcyc tsckh(2) +(10/3) tcyc tcyc data setup time tsdi(1) 2.5 to 5.5 0.03 serial input data hold time thdi(1) sb0(p11), si0(p11) ? must be specified with respect to rising edge of sioclk. ? see fig. 6. 2.5 to 5.5 0.03 tdd0(1) ? continuous data transmission/reception mode ? (note 4-1-3) 2.5 to 5.5 (1/3)tcyc +0.05 input clock tdd0(2) ? synchronous 8-bit mode ? (note 4-1-3) 2.5 to 5.5 1tcyc +0.05 serial output output clock output delay time tdd0(3) so0(p10), sb0(p11) (note 4-1-3) 2.5 to 5.5 (1/3)tcyc +0.05 s note 4-1-1: these specifications are theoretical values. add margin depending on its use. note 4-1-2: to use serial-clock-input in continuous trans/rec mode, a time from si0run being set when serial clock is "h" to the first negative edge of the serial clock must be longer than tsckha. note 4-1-3: must be specified with respect to falling edge of sioclk. must be specified as the time to the beginning of output state change in open drain output mode. see fig. 6.
LC87F5G32A no.8298-15/23 2. sio1 serial i/o characteristics (note 4-2-1) specification parameter symbol pin/remarks conditions v dd [v] min typ max unit frequency tsck(3) 2 low level pulse width tsckl(3) 1 input clock high level pulse width tsckh(3) sck1(p15) see fig. 6. 2.5 to 5.5 1 frequency tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1(p15) ? cmos output selected ? see fig. 6. 2.5 to 5.5 1/2 tsck data setup time tsdi(2) 2.5 to 5.5 0.03 serial input data hold time thdi(2) sb1(p14), si1(p14) ? must be specified with respect to rising edge of sioclk. ? see fig. 6. 2.5 to 5.5 0.03 serial output output delay time tdd0(4) so1(p13), sb1(p14) ? must be specified with respect to falling edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 6. 2.5 to 5.5 (1/3)tcyc +0.05 s note 4-2-1: these specifications are theoretical values. add margin depending on its use.
LC87F5G32A no.8298-16/23 pulse input conditions at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit tpih(1) tpil(1) int0(p70), int1(p71), int2(p72), int4(p20 to p23), int5(p24 to p27) ? interrupt source flag can be set. ? event inputs for timer 0 or 1 are enabled. 2.5 to 5.5 1 tpih(2) tpil(2) int3(p73) when noise filter time constant is 1/1 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.5 to 5.5 2 tpih(3) tpil(3) int3(p73) when noise filter time constant is 1/32 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.5 to 5.5 64 tpih(4) tpil(4) int3(p73) when noise filter time constant is 1/128 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.5 to 5.5 256 tcyc high/low level pulse width tpil(5) res resetting is enabled. 2.5 to 5.5 200 s ad converter characteristics at v ss 1 = v ss 2 = v ss 3 = 0v <12-bits ad converter mode / ta= -10 c to +50 c> specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 4.75 to 5.25 12 bit absolute accuracy et (note 6-1) 4.75 to 5.25 t.b.d lsb conversion time tcad see conversion time calculation formulas. (note 6-2) 4.75 to 5.25 38.5 90 s analog input voltage range vain 4.75 to 5.25 v ss v dd v iainh vain=v dd 4.75 to 5.25 1 analog port input current iainl an0(p00) to an7(p07) an8(p70) an9(p71) an10(xt1) an11(xt2) vain=v ss 4.75 to 5.25 -1 a <8-bits ad converter mode / ta= -30 c to +70 c> specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 8 bit absolute accuracy et (note 6-1) 3.0 to 5.5 1.5 lsb 4.5 to 5.5 22.5 90 conversion time tcad see conversion time calculation formulas. (note 6-2) 3.0 to 5.5 45 90 s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain=v dd 3.0 to 5.5 1 analog port input current iainl an0(p00) to an7(p07) an8(p70) an9(p71) an10(xt1) an11(xt2) vain=v ss 3.0 to 5.5 -1 a conversion time calculation formulas: 12-bits ad converter mode: tcad (conversion time) = ((52/(division ratio))+2) (1/3) tcyc 8-bits ad converter mode: tcad (conver sion time) = ((32/(division ratio))+2) (1/3) tcyc note 6-1: the quantization error ( 1/2lsb) must be excluded from the absolute accuracy. the absolute accuracy must be measured in the microcontroller's state in which no i/o operations occur at the pins adjacent to the analog input channel. note 6-2: the conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. the conversion time is 2 times the normal-time conversion time when: ? the first ad conversion is performed in the 12 -bit ad conversion mode after a system reset. ? the first ad conversion is performed after the ad conversion mode is switched from 8-bit to 12-bit conversion mode.
LC87F5G32A no.8298-17/23 consumption current characteristics at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit iddop(1) ? fmcf=10mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 10mhz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/1 frequency division ratio 4.0 to 5.5 7.7 20 iddop(2) ? cf1=20mhz external clock ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to cf1 side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/2 frequency division ratio 4.0 to 5.5 8.7 20 iddop(3) 4.5 to 5.5 5.2 12 iddop(4) ? fmcf=5mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 5mhz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/1 frequency division ratio 4.5 to 5.5 3.5 10 iddop(5) 4.5 to 5.5 0.7 2.9 iddop(6) ? fmcf=0hz (oscillation stopped) ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to internal rc oscillation ? frequency variable rc oscillation stopped ? 1/2 frequency division ratio 2.5 to 4.5 0.4 2.1 iddop(7) 4.5 to 5.5 1.4 5.3 iddop(8) ? fmcf=0hz (oscillation stopped) ? fsx?tal=32.768khz crystal oscillation mode ? internal rc oscillation stopped ? system clock set to 1mhz with frequency variable rc oscillation ? 1/2 frequency division ratio 2.5 to 4.5 0.9 3.9 ma iddop(9) 4.5 to 5.5 34 90 normal mode consumption current (note 7-1) iddop(10) v dd 1 =v dd 2 =v dd 3 ? fmcf=0hz (oscillation stopped) ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 32.768khz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/2 frequency division ratio 2.5 to 4.5 23 70 a note 7-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors. continued on next page.
LC87F5G32A no.8298-18/23 continued from preceding page. specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit iddhalt(1) ? halt mode ? fmcf=10mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 10mhz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/1 frequency division ratio 4.0 to 5.5 3.1 6 iddhalt(2) ? halt mode ? cf1=20mhz external clock ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to cf1 side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/2 frequency division ratio 4.0 to 5.5 4 9 iddhalt(3) 4.5 to 5.5 1.9 4.1 iddhalt(4) ? halt mode ? fmcf=5mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 5mhz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/1 frequency division ratio 2.5 to 4.5 1.3 3.0 iddhalt(5) 4.5 to 5.5 0.35 1.4 iddhalt(6) ? halt mode ? fmcf=0hz (oscillation stopped) ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to internal rc oscillation ? frequency variable rc oscillation stopped ? 1/2 frequency division ratio 2.5 to 4.5 0.25 0.95 iddhalt(7) 4.5 to 5.5 1.1 4 iddhalt(8) ? halt mode ? fmcf=0hz (oscillation stopped) ? fsx?tal=32.768khz crystal oscillation mode ? internal rc oscillation stopped ? system clock set to 1mhz with frequency variable rc oscillation ? 1/2 frequency division ratio 2.5 to 4.5 0.8 3.0 ma iddhalt(9) 4.5 to 5.5 20 51 halt mode consumption current (note 7-1) iddhalt(10) v dd 1 =v dd 2 =v dd 3 ? halt mode ? fmcf=0hz (oscillation stopped) ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 32.768khz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/2 frequency division ratio 2.5 to 4.5 18 35 iddhold(1) 4.5 to 5.5 0.04 11 hold mode consumption current iddhold(2) v dd 1 hold mode ? cf1=v dd or open (external clock mode) 2.5 to 4.5 0.01 8 iddhold(3) 4.5 to 5.5 17 50 timer hold mode consumption current iddhold(4) v dd 1 timer hold mode ? cf1=v dd or open (external clock mode) ? fsx?tal=32.768khz crystal oscillation mode 2.5 to 4.5 12 30 a note 7-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors.
LC87F5G32A no.8298-19/23 f-rom programming characteristics at ta = +10c to +55c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit onboard programming current iddfw v dd 1 ? 128-byte programming ? erasing current included 3.0 to 5.5 25 40 ma programming time tfw ? 128-byte programming ? erasing current included ? time for setting up 128-byte data is excluded. 3.0 to 5.5 22.5 45 ms uart (full duplex) op erating conditions at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit transfer rate ubr p20, p21 2.5 to 5.5 16/3 8192/3 tcyc data length: 7, 8, and 9 bits (lsb first) stop bits: 1-bit (2-bit in continuous data transmission) parity bits: non example of continuous 8-bit data transmission mode processing (first transmit data=55h) example of continuous 8-bit da ta reception mode processing (first receive data=55h) start bit stop bit transmit data (lsb first) start of transmission end of transmission ubr ubr receive data (lsb first) start of reception end of reception start bit stop bit
LC87F5G32A no.8298-20/23 characteristics of a sample main system clock oscillation circuit given below are the characteristics of a sample main syst em clock oscillation circuit that are measured using a sanyo-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 1 characteristics of a sample main system clock oscillator circuit with a ceramic oscillator circuit constant oscillation stabilization time nominal frequency vendor name oscillator name c1 [pf] c2 [pf] rf [ ? ] rd1 [ ? ] operating voltage range [v] typ [ms] max [ms] remarks cstce10m0g52-r0 (10) (10) open 680 4.0 to 5.5 0.1 0.5 10mhz murata cstce10m0g52-b0 (10) (10) open 680 4.0 to 5.5 0.1 0.5 internal c1, c2 (smd type) cstce8m00g52-r0 (10) (10) open 1.0k 3.0 to 5.5 0.1 0.5 8mhz murata cstce8m00g52-b0 (10) (10) open 1.0k 3.0 to 5.5 0.1 0.5 internal c1, c2 (smd type) cstcr5m00g53-r0 (15) (15) o pen 2.2k 2.5 to 5.5 0.2 0.6 5mhz murata cstcr5m00g53-b0 (15) (15) o pen 2.2k 2.5 to 5.5 0.2 0.6 internal c1, c2 (smd type) the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after v dd goes above the operating voltage lower limit (see figure 4). it is recommended to inse rt feedback resister(rf:1m ? ) when power supply voltage is used around 2.5v. characteristics of a sample subs ystem clock oscillator circuit given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a sanyo- designated oscillation characteristics evaluation board and exte rnal components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 2 characteristics of a sample subsystem cl ock oscillator circuit with a crystal oscillator circuit constant oscillation stabilization time nominal frequency vendor name oscillator name c3 [pf] c4 [pf] rf [ ? ] rd2 [ ? ] operating voltage range [v] typ [s] max [s] remarks 32.768khz epson toyocom mc-306 18 18 open 510k 2.5 to 5.5 1.1 3.0 applicable cl value=12.5pf the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is ex ecuted and to the time interval that is required for the oscillation to get stabilized after the hold mode is reset (see figure 4). note: the components that are in volved in oscillation should be placed as close to the ic an d to one another as possible because they are vulnerable to the influences of the circuit pattern. figure 1 cf oscillator circuit figure 2 xt oscillator circuit figure 3 ac timing measurement point 0.5v dd cf2 cf1 c3 rd2 c4 x?tal xt2 xt1 rf c1 rd1 c2 cf rf
LC87F5G32A no.8298-21/23 reset time and oscillation stabilization time hold reset signal and oscillation stabilization time figure 4 oscillation stabilization times operating v dd lower limit power suppl y res internal rc oscillation cf1, cf2 xt1, xt2 operating mode reset time tmscf tmsx?tal unpredictable reset instruction execution v dd 0v internal rc oscillation cf1, cf2 xt1, xt2 state hold reset signal hold release signal valid tmscf tmsx?tal hold halt hold reset signal absent
LC87F5G32A no.8298-22/23 figure 5 reset circuit figure 6 serial i/o output waveforms figure 7 pulse input timing signal waveform c res v dd r res res (note) determine the value of c res and r res so that the reset signal is present for a period of 200 s after the supply voltage goes beyond the lower limit of the ic's operating voltage. tpil tpih di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 sioclk : datain : dataout : dataout : datain : sioclk : dataout : datain : sioclk : tsck tsckl tsckh thdi tsdi tddo tsckl tsckha thdi tsdi tddo data ram transfer period (sio0 only) data ram transfer period (sio0 only)
LC87F5G32A no.8298-23/23 ps this catalog provides information as of january, 2007. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qu ality high-reliability pr oducts, however, any and all semiconductor products fail or malfunction with some proba bility. it is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damag e to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products descr ibed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co .,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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